Hi,

    It turns out that sub-micron CMOS is intrinsically radiation hard, provided there are some tweaks to the design rules.    Circuits designed in this way can withstand megarads, as demonstrated at CERN’s Large Hadron Collider (see e.g., https://www.osti.gov/pages/servlets/purl/1353115 ).  Designers at CERN flirted with exotic rad hard processes for several years, but ultimately abandoned them when it was realized that standard CMOS would work fine and be a lot easier to deal with.    The intrinsic hardness comes about because the main effect of radiation damage is charge build-up in the oxide layer (the “O” in CMOS), this causes transistor thresholds to shift in an unpredictable way, which ultimately causes circuits to fail.   As one goes to smaller feature sizes, however, everything gets smaller, including the thickness of the oxide layer and the attendant shifts.     Single event upset remains a problem, but can be dealt with (e.g.) by using 2 of 3 redundancy in the logic.        

    The good news is that one can use standard IC processes, but only if special design rules are employed.   That clearly means custom designs, which is not realistic when it comes to microcomputers.     One could, however, imagine designing a rad hard watchdog circuit using a relatively inexpensive multi-project wafer run, but I am not sure whether or not this would help.   

73,
Dan K2QM

From: Bruce Perens via AMSAT-BB <[email protected]>
Reply-To: Bruce Perens <[email protected]>
Date: Sunday, January 31, 2021 at 3:13 PM
To: David Spoelstra <[email protected]>
Cc: Robert Bruninga <[email protected]>, Ray Soifer <[email protected]>, "[email protected]" <[email protected]>
Subject: [AMSAT-BB] Radiation and Cubesats

We could talk about radiation for a long time, and I'm not an expert, so I'll just bring up a few points.

Our LEO satellites in equatorial orbits are not in a harsh radiation environment. Satellites that traverse the van Allen belts, or are in a polar orbit, are.

What makes a semiconductor "rad hard" or not? The main problem is that radiation can cause unwanted conductivity across a semiconductor junction. And rather than an intended junction, it's often between some IC detail and the substrate. And once conduction starts, it may require removal of power to stop it if you're lucky. If you aren't lucky, overcurrent blows that detail off of the IC.

So, for radiation hardness, ICs are fabricated upon an insulating substrate, rather than a semiconducting one.

This was the origin of the silicon on sapphire chips, which were incredibly expensive. These days silicon on insulator is used, and can be just as expensive because they may be fabricated in small runs without economies of scale.

However, some chips are already fabricated on insulator as part of their regular process. A number of modern CPU/gate-array combinations are, and are available at decent prices.

Once one eliminates the substrate issues, there is still the issue of radiation across intended junctions. This is in general handled by various sorts of redundancy, and sometimes the ability to power-down the IC.

Historically, AMSAT used a silicon-on-sapphire 1802 CPU which was not booted from a ROM. It was booted by a hardware modem from a ground upload. So, this could not be "bricked" as long as the hardware was intact and working. The OS would continually scrub the memory pages with a read-correct-write cycle.

Modern CPUs are more complicated and often less reliable. There was once even a project to fly a cell phone! Giving these things a simpler bootstrap processor, which could take over if they failed, might be a good idea.

And if your satellite can't recover if launched with a dead battery, IMO you asked for the problem.