Low frquencies will be dominated by the multiplied reference oscillator noise and high frequencies by the VCO free-running noise with an area of relatively flat phase noise in between. The simulation I've done may not be as accurate as possible as phase detector noise isn't specified for the SoI PLL ICs being used. However it may be easier to determine whether the existing design is adequate for the text-mode uplinks rather than come up with a general model.
73
John KD6OZH
----- Original Message ----- From: "Grant Hodgson" [email protected] To: "Phil Karn" [email protected] Cc: "EAGLE" [email protected] Sent: Wednesday, January 10, 2007 10:51 UTC Subject: [eagle] LO Phase noise (was : TeamSpeak conference for Tuesday 16Jan)
Phil Karn wrote:
--snip---
I was going to model phase noise as 1/f^2, but Bob pointed out that the integral of that expression bounded at zero (DC) is undefined. So we need another, more realistic model of oscillator phase noise if we're going to compute its effect on digital demodulation.
--Phil
This is a paradox which AFAIK has not yet been resolved properly. Assuming a low frequency cut-off of 1Hz as has been suggested is not ideal, but given that most oscillator manufacturers don't specify phase noise below this offset it is a reasonable compromise in practice.
However the 1/f^2 model is only valid above the flicker corner frequency, below which the noise rises at 1/f^3 to an undefined point where it rises at 1/f^4 due to 'random walk'. At very high frequency offsets the 1/f^2 term disappears and the noise becomes white, or gaussian, the level remaining constant with offset frequency. The flicker corner frequency could be as high as 100Hz or more, and so cannot be ignored. And this simple model applies only to free-running oscillators...
The 70cms Rx LO uses two Phase-locked loops. The noise behavior of a PLL is somewhat more complex than a simple free running oscillator. At frequency offsets greater than the loop bandwidth, the noise of the oscillator (i.e. VCO) dominates, making the analysis relatively simple. At offset frequencies close to and less than the loop bandwidth, many factors affect the noise behavior, all of which need to be considered. Fortunately analysis tools are available free from a number of sources which do a pretty good job of simulating the PLL phase noise for most practical offset frequencies. I don't know if a detailed PLL phase noise analysis has been done, I couldn't find one in EP.
As the two Rx LOs are independent, the total noise contribution will be non-coherent and can simply be added together. This is actually a simplification, as I believe that the reference for both PLLs is common, but this simplification should be OK.
Also, for digital systems one of the key parameters is the RMS phase error. Depending on what type of modulation is used (as well as the Rx S/N ratio), this parameter can have a significant effect on the system BER. The RMS phase error is an integral of the phase noise between two defined offsets and is easy to calculate, once the frequency distribution of the phase noise has been calculated.
regards
Grant G8UBN _______________________________________________ Via the Eagle mailing list courtesy of AMSAT-NA [email protected] http://amsat.org/mailman/listinfo/eagle