26 Mar
2007
26 Mar
'07
11:07 p.m.
John B. Stephensen wrote:
The big current spike is during start up and the static current afterwards is low enough so that you can manage power dissiation.
Simply not true. Large 65nm FPGAs dissipate several watts of standby power.
I wouldn't use DCMs for the reciver as it must deal with multiple narrow-bandwidth signals. The downlink will be about 2 Mbaud BPSK so phase noise isn't a big issue in generating low-frequency signals to be upconverted.
I can speak from experience here. Clocks coming out of the FPGA are simply not clean enough to use for this purpose.
Matt