I do not think this is right. I believe we discussed the ACP experiment and believe that we need heat sink module to handle the FPGA's heat engines in it.
Lyle and I have not discussed the FPGA in the SDX experiment which will be used to generator the polar representation of the baseband signal and some other processing to be passed out to the HELAPS drivers, amplifiers and modulators. I do not believe we have a heat budget yet for that part at full speed but I am expecting it to not be high.
The ACP will have two FPGA's in it probably, one for TX and one for RX. These processors will be 10w total in our best guesstimate at the current state of technology. The ACP does not have a design yet.
The TI part should not be toasty and the RAM will not be toasty. I think this note is wrong given my current understanding of the technologies involved. If I said SDX, I was not being careful.
I have been on the road and away from home for many days except for two periods under 24 hours. I have not been returning many phone calls and emails and I apologize. I will return home on Thursday at which time I am informed by my boss (N2HPE) that I need a long break. ;-) My apologies to one and all.
73's
Bob N4HY
Dick Jansson-rr wrote:
Howard:
Some time ago, Bob McGwier and I discussed the SDX thermal issue and pretty well decided that this module would need to be one of our heat sink module designs, either E05 25 or if you need it larger the E05 15 module. These will be specially treated in their mounting in the spacecraft and not be thermally isolated from the spaceframe as the other, non-power modules are handled. In this module the power devices are clamped directly to the heat sink using a space-rated thermal compound at their interfaces. The interfacing of devices such as the PowerPAD from TI, will need some study of the papers that you have referenced. That will not obviate the treatment of the module as a power device, however. I shall be back to you on this. In the meantime, please take the time to study the drawings on these modules so that you become familiar with this design.
Dick Jansson, KD1K (ex: WD4FAB) [email protected]
-----Original Message----- From: Howard Long [mailto:[email protected]] Sent: Tuesday, 20 February, 2007 1117 To: 'Dick Jansson-rr'; 'AMSAT Eagle ' Subject: RE: [eagle] URx
Hi Dick, John,
Device Dissipation Delivered U16 0.340 0.850 U17 0.411 U18 0.384 1.200 U19 0.108 0.090 U20 0.040 0.224 ------------ ------------ Totals 1.283W 2.364W
For a grand total power dissipation of the power system of 3.647W.
I am particularly interested in this as the DSP device on the SDX (TMS320C6726) typically dissipates 857mW at its full 250MHz speed. It is a 144 pin LQFP PowerPad device and has a metal plate directly underneath the die that is designed to be soldered directly to the PCB ground plane.
In order to conduct heat away, TI recommend the optimum to be 100 0.33mm vias in a 10x10 matrix.
See http://www.g6lvb.com/dspthermal.jpg for the design I developed for the prototype I use for my software development.
We will almost certainly need to conduct heat away from the device on the underside, so that would suggest to me a direct metallic interface between the board and the module housing, either milled out of the chassis itself or with an interfacing block. IT should be noted that for electrical reasons there are also 44 decupling capacitors on the bottom of the PCB that need to be considered when providing the thermal interface.
We also would need some space rated goo to ensure good thermal conductivity between the PCB and the heatsink - I am sure someone will know what this is!
One final thing - 3.647W seems very high for the receiver function. Is this based on real figures or device spec sheets, and if the latter are these worst case or typical values?
73, Howard G6LVB
PowerPADT Thermally Enhanced Package http://focus.ti.com/lit/an/slma002a/slma002a.pdf
PowerPADT Layout Guidelines http://focus.ti.com/lit/an/sloa120/sloa120.pdf
PowerPADT Made Easy http://www-s.ti.com/sc/psheets/slma004b/slma004b.pdf
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