I have (finally!) put the finishing touches on my magnum opus describing my ideas on phased arrays and shipped it off to be included in the Pittsburgh symposium proceedings. If you want to see it, it is available for viewing at http://mysite.verizon.net/w3iwi/electronic_scanning_antennas.pdf. This version has some figures in color, but the proceedings is in B&W (this format is available if you need it).
This took me a lot longer than I anticipated. I had a couple of fairly major Gates-induced computer failures, some of which still plague me (like I'm using my notebook for all Email). I advise against the use of Office 2007.
I am hoping that this week I will have time to test Dan's hardware so I can have some results to report by Pittsburgh.
Matt -- this has the numbers I was trying to remember last weekend.
For all -- your comments and critiques are solicited.
73, Tom
Tom,
I have the working simulation of the tapped delay line design. I did all my sims with a delay line spacing of 30mm per element, or 0.3 wavelengths at 300 MHz. Some observations:
- Once the varactor capacitance gets high enough, you start to get reflections which mess up the phasing. It happens to the elements nearest to the generator (center of the array) first. At 300 MHz, you get bad behavior at the center, first, and second elements if the capacitance gets over about 0.8 pF. Going to a lower frequency will allow for more capacitance, but you will need longer delay lines, and will then end up with the same problem.
- The tap for getting the signal out may add capacitance of about the same order of magnitude.
- The delay line needs to be long enough, or the caps all look like they are in parallel.
- The center element will be common to all 12 strings, so some method of splitting is necessary. This splitting will introduce a phase offset which is not linear with the applied voltage, so it will need to be compensated for by changing the length of the delay lines between the center element and the first varactor.
- You can probably reduce the reflections by putting attenuators in the delay lines, but these would make the DC biasing of the varactors more difficult.
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
Matt
Tom Clark, K3IO wrote:
I have (finally!) put the finishing touches on my magnum opus describing my ideas on phased arrays and shipped it off to be included in the Pittsburgh symposium proceedings. If you want to see it, it is available for viewing at http://mysite.verizon.net/w3iwi/electronic_scanning_antennas.pdf. This version has some figures in color, but the proceedings is in B&W (this format is available if you need it).
This took me a lot longer than I anticipated. I had a couple of fairly major Gates-induced computer failures, some of which still plague me (like I'm using my notebook for all Email). I advise against the use of Office 2007.
I am hoping that this week I will have time to test Dan's hardware so I can have some results to report by Pittsburgh.
Matt -- this has the numbers I was trying to remember last weekend.
For all -- your comments and critiques are solicited.
73, Tom
<Qucs Schematic 0.0.12> <Properties> <View=40,-14,1338,912,0.9689,0,87> <Grid=10,10,1> <DataSet=simple_phaser.dat> <DataDisplay=simple_phaser.dpl> <OpenDisplay=0> <showFrame=0> <FrameText0=Title> <FrameText1=Drawn By:> <FrameText2=Date:> <FrameText3=Revision:> </Properties> <Symbol> </Symbol> <Components> <TLIN Line4 1 650 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <GND * 1 110 250 0 0 0 0> <Pac P1 1 110 180 18 -26 0 1 "1" 1 "50 Ohm" 1 "0 dBm" 0 "1 GHz" 0 "26.85" 0> <TLIN Line5 1 220 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line1 1 330 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line2 1 440 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line3 1 550 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <GND * 1 930 240 0 0 0 0> <Pac P2 1 930 170 18 -26 0 1 "2" 1 "50 Ohm" 1 "0 W" 0 "1 GHz" 0 "26.85" 0> <TLIN Line6 1 750 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line7 1 850 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <.AC AC1 1 100 310 0 49 0 0 "lin" 1 "0.2 GHz" 1 "0.4 GHz" 1 "100" 1 "no" 0> <GND * 1 280 270 0 0 0 0> <GND * 1 390 270 0 0 0 0> <GND * 1 500 270 0 0 0 0> <GND * 1 600 270 0 0 0 0> <GND * 1 700 270 0 0 0 0> <GND * 1 800 270 0 0 0 0> <.SW SW1 1 90 520 0 83 0 0 "AC1" 1 "lin" 1 "C1" 1 "0pF" 1 "2pF" 1 "5" 1> <C C1 1 280 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C2 1 390 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C3 1 500 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C4 1 600 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C5 1 700 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C6 1 800 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <Eqn Eqn1 1 330 320 -32 19 0 0 "phase_p1=angle(p1.v)" 1 "phase_p2=angle(p2.v)" 1 "phase_p3=angle(p3.v)" 1 "phase_p4=angle(p4.v)" 1 "phase_p5=angle(p5.v)" 1 "phase_p6=angle(p6.v)" 1 "phase_p7=angle(p7.v)" 1 "yes" 0> <.SP SP1 0 530 310 0 83 0 0 "lin" 1 "0.1 GHz" 1 "0.4 GHz" 1 "100" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0> <.SW SW2 0 530 530 0 83 0 0 "SP1" 1 "lin" 1 "C1" 1 "0.5pF" 1 "3pF" 1 "4" 1> <Eqn Eqn2 0 330 570 -32 19 0 0 "s11_db=dB(S[1,1])" 1 "s22_db=dB(S[2,2])" 1 "yes" 0> </Components> <Wires> <110 210 110 250 "" 0 0 0 ""> <110 110 110 150 "" 0 0 0 ""> <110 110 190 110 "p1" 170 60 18 ""> <250 110 280 110 "p2" 280 60 0 ""> <360 110 390 110 "" 0 0 0 ""> <580 110 600 110 "" 0 0 0 ""> <470 110 500 110 "" 0 0 0 ""> <930 200 930 240 "" 0 0 0 ""> <680 110 700 110 "p6" 710 60 9 ""> <780 110 800 110 "p7" 830 60 17 ""> <880 110 930 110 "" 0 0 0 ""> <930 110 930 140 "" 0 0 0 ""> <280 250 280 270 "" 0 0 0 ""> <280 110 300 110 "" 0 0 0 ""> <280 110 280 190 "" 0 0 0 ""> <390 250 390 270 "" 0 0 0 ""> <390 110 410 110 "p3" 440 50 20 ""> <390 110 390 190 "" 0 0 0 ""> <500 250 500 270 "" 0 0 0 ""> <500 110 520 110 "p4" 540 60 15 ""> <500 110 500 190 "" 0 0 0 ""> <600 250 600 270 "" 0 0 0 ""> <600 110 620 110 "p5" 640 60 5 ""> <600 110 600 190 "" 0 0 0 ""> <700 250 700 270 "" 0 0 0 ""> <700 110 720 110 "" 0 0 0 ""> <700 110 700 190 "" 0 0 0 ""> <800 250 800 270 "" 0 0 0 ""> <800 110 820 110 "" 0 0 0 ""> <800 110 800 190 "" 0 0 0 ""> </Wires> <Diagrams> <Rect 670 780 240 160 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" ""> <"s11_db" #0000ff 0 3 0 0 0> <"s22_db" #ff0000 0 3 0 0 0> </Rect> <Rect 980 646 301 326 3 #c0c0c0 1 00 1 2e+08 5e+07 4e+08 1 -2.34563 0.5 0.5 1 -1 0.5 1 315 0 225 "" "" ""> <"phase_p1" #0000ff 0 3 0 0 0> <"phase_p2" #ff0000 0 3 0 0 0> <"phase_p3" #ff00ff 0 3 0 0 0> <"phase_p4" #00ff00 0 3 0 0 0> <"phase_p5" #00ffff 0 3 0 0 0> <"phase_p6" #ff5500 0 3 0 0 0> <"phase_p7" #000000 0 3 0 0 0> </Rect> </Diagrams> <Paintings> </Paintings>
Matt Ettus wrote:
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
The qucs version distributed in Ubuntu Feisty is 0.0.9. The schematic appears to be using features that require a more recent edition; the latest is 0.0.12.
73 Frank AB2KT
Frank Brickle wrote:
Matt Ettus wrote:
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
The qucs version distributed in Ubuntu Feisty is 0.0.9. The schematic appears to be using features that require a more recent edition; the latest is 0.0.12.
I used 0.0.11 and 0.0.12. 0.0.12 is part of Fedora 6 and 7.
Matt
Matt Ettus wrote:
I have the working simulation of the tapped delay line design. I did all my sims with a delay line spacing of 30mm per element, or 0.3 wavelengths at 300 MHz. Some observations:
- Once the varactor capacitance gets high enough, you start to get
reflections which mess up the phasing. It happens to the elements nearest to the generator (center of the array) first. At 300 MHz, you get bad behavior at the center, first, and second elements if the capacitance gets over about 0.8 pF. Going to a lower frequency will allow for more capacitance, but you will need longer delay lines, and will then end up with the same problem.
Yes, at 300 MHz, 0.8 pf has a capacitive reactance of 660 ohms. That value will induce a return loss of about -11 dB (VSWR ~1.1:1). Part of the requirement is that the frequency be chosen such that the reflections don't add up badly. One idea that I plan to try is to choose the lengths such that each cable is an odd number of quarter wavelengths. This should allow a cancellation of the reflections.
- The tap for getting the signal out may add capacitance of about the
same order of magnitude.
The signal extraction tap in the test fixture is 10k, so its reflection is negligible.
- The delay line needs to be long enough, or the caps all look like they
are in parallel.
Agree
- The center element will be common to all 12 strings, so some method of
splitting is necessary. This splitting will introduce a phase offset which is not linear with the applied voltage, so it will need to be compensated for by changing the length of the delay lines between the center element and the first varactor.
This was always in the plan, although I chose to omit the detail in the paper for simplicity.
- You can probably reduce the reflections by putting attenuators in the
delay lines, but these would make the DC biasing of the varactors more difficult.
My model has assumed ~1 dB of loss intrinsic in each coax line, and I see you used lossless lines. It may also be necessary to put a resistor in series with the varactor to help with the reflections.
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
Following your tip last weekend, I picked up QUCS from SourceForge. Nifty program. I have had trouble doing a sim at a constant frequency with a variable capacitor. Your example gave me some hints, but I still have problems doing a sim under such conditions. I'm learning!
Dick also made these comments:
You present a very interesting paper for the Symposium. What is your next step? When are you going to construct a test bread board of an array? To do this you need an amplifier concept as an element of the antenna. In the recent past (~2 years) we started such an amplifier examination but the effort withered, apparently, and not much came of it as I remember. I recognize that there are a number of closely related electronic, mechanical, and thermal issues for such an amplifier element, along with Dan’s delay line and other aspects.
Dick -- the task I took on was as an architect/physicist. I set my goal as defining the concept, not doing the detailed design. As such, I have tried to figure out how the critical components should work. My next step at that level is to test the basic phasing concept to see if my idea works. I had hoped to be at that point already, but I have problems with round tuit procurement!
As I see it, getting started in such an amplifier element, now that you have a concept for the beam steering, is just as important to the Eagle project as is such work that has been done recently on the U receiver by John and Juan. I realize that the electronic aspects of such hardware is somewhat of a moving target (the pace of developments in that field), but somewhere you will have to put a stake in the ground and say that this is where we shall start. To be able to deal with the mechanical and thermal aspects, which are not trivial at all, I would need you to put the stake in the ground so that I would have a starting point for such an effort.
No disagreement. I hope that this paper will serve as a probe for the real RF designers. The big change from our earlier discussions on amplifiers is that we seem to have reached agreement that the microwave PAs can be hard limiting which will have a BIG impact on power consumption and heat loading.
However, until we have a real schedule that is focussed on a real launch opportunity, I believe the volunteers (including me) devote less than the necessary 110% effort to the problem. I'm really hoping that Rick will be able to make such an announcement at Pittsburgh. Then things will really start moving.
For all -- Dan asked me to reformat the paper's margins for the proceedings. As a result, the "final" version posted at http://mysite.verizon.net/w3iwi/electronic_scanning_antennas.pdf (those are _ characters separating the words) has grown from 17 to 20 pages in length, with no change in content except for the repair of some minor typos.
73, Tom
Yes, at 300 MHz, 0.8 pf has a capacitive reactance of 660 ohms. That value will induce a return loss of about -11 dB (VSWR ~1.1:1). Part of the requirement is that the frequency be chosen such that the reflections don't add up badly. One idea that I plan to try is to choose the lengths such that each cable is an odd number of quarter wavelengths. This should allow a cancellation of the reflections.
- The tap for getting the signal out may add capacitance of about the
same order of magnitude.
The signal extraction tap in the test fixture is 10k, so its reflection is negligible.
The pads on the PCB for the 10K resistor will have some capacitance. Unless you are careful, they can be an appreciable fraction of a pF.
- You can probably reduce the reflections by putting attenuators in the
delay lines, but these would make the DC biasing of the varactors more difficult.
My model has assumed ~1 dB of loss intrinsic in each coax line, and I see you used lossless lines. It may also be necessary to put a resistor in series with the varactor to help with the reflections.
I can try simulating with the series resistor, but my gut says it will mess up the linearity of the phasing vs. tap. 1dB of loss per section of coax might help. I'll try simulating it. I don't know if we can count on that much loss from such a short piece of coax at these frequencies, though. High loss coax might not help, since loss would mostly come from leakage, not absorption, which would be a problem.
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
Following your tip last weekend, I picked up QUCS from SourceForge. Nifty program. I have had trouble doing a sim at a constant frequency with a variable capacitor. Your example gave me some hints, but I still have problems doing a sim under such conditions. I'm learning!
I don't know how to make it NOT sweep frequency. However, you can make the start and stop frequency the same, and use only 2 points. Then you can make the capacitance value into the independent axis of the graphs.
If there is anything else you'd like me to simulate, let me know.
Matt
Would an inductor in series with each varactor help? The total reactance can then vary from a positive value, through zero to a negative value so that a greater phase variation might be acheived with lower reflections.
73,
John KD6OZH
----- Original Message ----- From: "Matt Ettus" matt@ettus.com To: K3IO@verizon.net Cc: "AMSAT Eagle" Eagle@amsat.org; "'Brian E. Gaffney'" beg@bellatlantic.net; "Daniel Schultz" n8fgv@usa.net Sent: Sunday, October 07, 2007 06:47 UTC Subject: [eagle] Re: Phased Array Concepts
Tom,
I have the working simulation of the tapped delay line design. I did all my sims with a delay line spacing of 30mm per element, or 0.3 wavelengths at 300 MHz. Some observations:
- Once the varactor capacitance gets high enough, you start to get
reflections which mess up the phasing. It happens to the elements nearest to the generator (center of the array) first. At 300 MHz, you get bad behavior at the center, first, and second elements if the capacitance gets over about 0.8 pF. Going to a lower frequency will allow for more capacitance, but you will need longer delay lines, and will then end up with the same problem.
- The tap for getting the signal out may add capacitance of about the
same order of magnitude.
- The delay line needs to be long enough, or the caps all look like they
are in parallel.
- The center element will be common to all 12 strings, so some method of
splitting is necessary. This splitting will introduce a phase offset which is not linear with the applied voltage, so it will need to be compensated for by changing the length of the delay lines between the center element and the first varactor.
- You can probably reduce the reflections by putting attenuators in the
delay lines, but these would make the DC biasing of the varactors more difficult.
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
Matt
Tom Clark, K3IO wrote:
I have (finally!) put the finishing touches on my magnum opus describing my ideas on phased arrays and shipped it off to be included in the Pittsburgh symposium proceedings. If you want to see it, it is available for viewing at http://mysite.verizon.net/w3iwi/electronic_scanning_antennas.pdf. This version has some figures in color, but the proceedings is in B&W (this format is available if you need it).
This took me a lot longer than I anticipated. I had a couple of fairly major Gates-induced computer failures, some of which still plague me (like I'm using my notebook for all Email). I advise against the use of Office 2007.
I am hoping that this week I will have time to test Dan's hardware so I can have some results to report by Pittsburgh.
Matt -- this has the numbers I was trying to remember last weekend.
For all -- your comments and critiques are solicited.
73, Tom
--------------------------------------------------------------------------------
<Qucs Schematic 0.0.12>
<Properties> <View=40,-14,1338,912,0.9689,0,87> <Grid=10,10,1> <DataSet=simple_phaser.dat> <DataDisplay=simple_phaser.dpl> <OpenDisplay=0> <showFrame=0> <FrameText0=Title> <FrameText1=Drawn By:> <FrameText2=Date:> <FrameText3=Revision:> </Properties> <Symbol> </Symbol> <Components> <TLIN Line4 1 650 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <GND * 1 110 250 0 0 0 0> <Pac P1 1 110 180 18 -26 0 1 "1" 1 "50 Ohm" 1 "0 dBm" 0 "1 GHz" 0 "26.85" 0> <TLIN Line5 1 220 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line1 1 330 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line2 1 440 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line3 1 550 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <GND * 1 930 240 0 0 0 0> <Pac P2 1 930 170 18 -26 0 1 "2" 1 "50 Ohm" 1 "0 W" 0 "1 GHz" 0 "26.85" 0> <TLIN Line6 1 750 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <TLIN Line7 1 850 110 -26 20 0 0 "50 Ohm" 1 "30 mm" 1 "0 dB" 0 "26.85" 0> <.AC AC1 1 100 310 0 49 0 0 "lin" 1 "0.2 GHz" 1 "0.4 GHz" 1 "100" 1 "no" 0> <GND * 1 280 270 0 0 0 0> <GND * 1 390 270 0 0 0 0> <GND * 1 500 270 0 0 0 0> <GND * 1 600 270 0 0 0 0> <GND * 1 700 270 0 0 0 0> <GND * 1 800 270 0 0 0 0> <.SW SW1 1 90 520 0 83 0 0 "AC1" 1 "lin" 1 "C1" 1 "0pF" 1 "2pF" 1 "5" 1> <C C1 1 280 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C2 1 390 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C3 1 500 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C4 1 600 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C5 1 700 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <C C6 1 800 220 17 -26 0 1 "C1" 1 "" 0 "neutral" 0> <Eqn Eqn1 1 330 320 -32 19 0 0 "phase_p1=angle(p1.v)" 1 "phase_p2=angle(p2.v)" 1 "phase_p3=angle(p3.v)" 1 "phase_p4=angle(p4.v)" 1 "phase_p5=angle(p5.v)" 1 "phase_p6=angle(p6.v)" 1 "phase_p7=angle(p7.v)" 1 "yes" 0> <.SP SP1 0 530 310 0 83 0 0 "lin" 1 "0.1 GHz" 1 "0.4 GHz" 1 "100" 1 "no" 0 "1" 0 "2" 0 "no" 0 "no" 0> <.SW SW2 0 530 530 0 83 0 0 "SP1" 1 "lin" 1 "C1" 1 "0.5pF" 1 "3pF" 1 "4" 1> <Eqn Eqn2 0 330 570 -32 19 0 0 "s11_db=dB(S[1,1])" 1 "s22_db=dB(S[2,2])" 1 "yes" 0> </Components> <Wires> <110 210 110 250 "" 0 0 0 ""> <110 110 110 150 "" 0 0 0 ""> <110 110 190 110 "p1" 170 60 18 ""> <250 110 280 110 "p2" 280 60 0 ""> <360 110 390 110 "" 0 0 0 ""> <580 110 600 110 "" 0 0 0 ""> <470 110 500 110 "" 0 0 0 ""> <930 200 930 240 "" 0 0 0 ""> <680 110 700 110 "p6" 710 60 9 ""> <780 110 800 110 "p7" 830 60 17 ""> <880 110 930 110 "" 0 0 0 ""> <930 110 930 140 "" 0 0 0 ""> <280 250 280 270 "" 0 0 0 ""> <280 110 300 110 "" 0 0 0 ""> <280 110 280 190 "" 0 0 0 ""> <390 250 390 270 "" 0 0 0 ""> <390 110 410 110 "p3" 440 50 20 ""> <390 110 390 190 "" 0 0 0 ""> <500 250 500 270 "" 0 0 0 ""> <500 110 520 110 "p4" 540 60 15 ""> <500 110 500 190 "" 0 0 0 ""> <600 250 600 270 "" 0 0 0 ""> <600 110 620 110 "p5" 640 60 5 ""> <600 110 600 190 "" 0 0 0 ""> <700 250 700 270 "" 0 0 0 ""> <700 110 720 110 "" 0 0 0 ""> <700 110 700 190 "" 0 0 0 ""> <800 250 800 270 "" 0 0 0 ""> <800 110 820 110 "" 0 0 0 ""> <800 110 800 190 "" 0 0 0 ""> </Wires> <Diagrams> <Rect 670 780 240 160 3 #c0c0c0 1 00 1 0 0.2 1 1 -0.1 0.5 1.1 1 -0.1 0.5 1.1 315 0 225 "" "" ""> <"s11_db" #0000ff 0 3 0 0 0> <"s22_db" #ff0000 0 3 0 0 0> </Rect> <Rect 980 646 301 326 3 #c0c0c0 1 00 1 2e+08 5e+07 4e+08 1 -2.34563 0.5 0.5 1 -1 0.5 1 315 0 225 "" "" ""> <"phase_p1" #0000ff 0 3 0 0 0> <"phase_p2" #ff0000 0 3 0 0 0> <"phase_p3" #ff00ff 0 3 0 0 0> <"phase_p4" #00ff00 0 3 0 0 0> <"phase_p5" #00ffff 0 3 0 0 0> <"phase_p6" #ff5500 0 3 0 0 0> <"phase_p7" #000000 0 3 0 0 0> </Rect> </Diagrams> <Paintings> </Paintings>
--------------------------------------------------------------------------------
Via the Eagle mailing list courtesy of AMSAT-NA Eagle@amsat.org http://amsat.org/mailman/listinfo/eagle
Long delayed response here ---
An inductor would not help. The problem occurs when the capacitance is too big -- i.e. when the reactance approaches zero. An inductor would allow us to cross zero reactance, but that's where we don't want to be -- at zero reactance we create a short and very bad reflections.
Matt
PS I had to cancel my trip to the symposium at the last minute. Bob will give my presentation. Have fun everyone.
John B. Stephensen wrote:
Would an inductor in series with each varactor help? The total reactance can then vary from a positive value, through zero to a negative value so that a greater phase variation might be acheived with lower reflections.
73,
John KD6OZH
----- Original Message ----- From: "Matt Ettus" matt@ettus.com To: K3IO@verizon.net Cc: "AMSAT Eagle" Eagle@amsat.org; "'Brian E. Gaffney'" beg@bellatlantic.net; "Daniel Schultz" n8fgv@usa.net Sent: Sunday, October 07, 2007 06:47 UTC Subject: [eagle] Re: Phased Array Concepts
Tom,
I have the working simulation of the tapped delay line design. I did all my sims with a delay line spacing of 30mm per element, or 0.3 wavelengths at 300 MHz. Some observations:
- Once the varactor capacitance gets high enough, you start to get
reflections which mess up the phasing. It happens to the elements nearest to the generator (center of the array) first. At 300 MHz, you get bad behavior at the center, first, and second elements if the capacitance gets over about 0.8 pF. Going to a lower frequency will allow for more capacitance, but you will need longer delay lines, and will then end up with the same problem.
- The tap for getting the signal out may add capacitance of about the
same order of magnitude.
- The delay line needs to be long enough, or the caps all look like they
are in parallel.
- The center element will be common to all 12 strings, so some method of
splitting is necessary. This splitting will introduce a phase offset which is not linear with the applied voltage, so it will need to be compensated for by changing the length of the delay lines between the center element and the first varactor.
- You can probably reduce the reflections by putting attenuators in the
delay lines, but these would make the DC biasing of the varactors more difficult.
I have attached my simulation. It was done in qucs, which runs on linux. See qucs.sf.net or get it from your distribution.
Matt
Tom:
You present a very interesting paper for the Symposium. What is your next step? When are you going to construct a test bread board of an array? To do this you need an amplifier concept as an element of the antenna. In the recent past (~2 years) we started such an amplifier examination but the effort withered, apparently, and not much came of it as I remember. I recognize that there are a number of closely related electronic, mechanical, and thermal issues for such an amplifier element, along with Dan's delay line and other aspects.
As I see it, getting started in such an amplifier element, now that you have a concept for the beam steering, is just as important to the Eagle project as is such work that has been done recently on the U receiver by John and Juan. I realize that the electronic aspects of such hardware is somewhat of a moving target (the pace of developments in that field), but somewhere you will have to put a stake in the ground and say that this is where we shall start. To be able to deal with the mechanical and thermal aspects, which are not trivial at all, I would need you to put the stake in the ground so that I would have a starting point for such an effort.
So what are your plans?
'73, Dick Jansson, KD1K mailto:kd1k@amsat.org kd1k@amsat.org mailto:kd1k@arrl.net kd1k@arrl.net
-----Original Message----- From: eagle-bounces@amsat.org [mailto:eagle-bounces@amsat.org] On Behalf Of Tom Clark, K3IO Sent: Sunday, 07 October, 2007 04.11 To: AMSAT Eagle; Matt Ettus Cc: 'Brian E. Gaffney'; Daniel Schultz Subject: [eagle] Phased Array Concepts
I have (finally!) put the finishing touches on my magnum opus describing my ideas on phased arrays and shipped it off to be included in the Pittsburgh symposium proceedings. If you want to see it, it is available for viewing at http://mysite.verizon.net/w3iwi/electronic_scanning_antennas.pdf . This version has some figures in color, but the proceedings is in B&W (this format is available if you need it).
This took me a lot longer than I anticipated. I had a couple of fairly major Gates-induced computer failures, some of which still plague me (like I'm using my notebook for all Email). I advise against the use of Office 2007.
I am hoping that this week I will have time to test Dan's hardware so I can have some results to report by Pittsburgh.
Matt -- this has the numbers I was trying to remember last weekend.
For all -- your comments and critiques are solicited.
73, Tom
participants (5)
-
Dick Jansson-rr -
Frank Brickle -
John B. Stephensen -
Matt Ettus -
Tom Clark, K3IO