Get MRAM size reports 512 which is 512 x 8 so 4 meg.
Test MRAM seems to be working.
On Feb 8, 2024, at 4:47 PM, Bob Stricklin via pacsat-dev pacsat-dev@amsat.org wrote:
<IMG_0005.jpeg>
Ok, I did clean project. Rebuild and load. The clear MRAM
See 4 now.
Bob On Feb 8, 2024, at 4:40 PM, Burns Fisher (AMSAT) via pacsat-dev pacsat-dev@amsat.org wrote:
It IS seeing 4 chips. It is getting values that are not 0xff. I think this is very promising! Try get mram size too! 73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Thu, Feb 8, 2024 at 5:38 PM Bob Stricklin via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote: <IMG_0004.jpeg>
I see version is q so I think this is most current. Not seeing 4 chips yet.
Bob On Feb 8, 2024, at 4:01 PM, Burns
Fisher (AMSAT) via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote:
Ok, please also get X0.1q (just pushed upstream).
I may have said before that I got one MRAM to work on my board. Now I have changed a few things so that it seems to do at least some of the tests correctly. I'm not 100% sure if it will work with only 1 and 4 chips or if it will work with yours as well. But anyway, it is an improvement. Do "clear mram" first.
Pacsat>get mram sr MRAM0: status ff, MRAM1: status 32 MRAM2: status ff, MRAM3: status ff
Pacsat>clear mram Post Launch Time Set to 2 minutesSet to start in safe mode WOD Frequency,size set to Default, and WOD Indices initialized Telemetry min/max in MRAM initialized Reset Count set to 0 Nonfatal error count zeroed (TBD) CRC calculated for init code and full code (TBD) MRAM Version Number Initialized MRAM config partition size is 1008 bytes MRAM file partition 1 size is 523280
Pacsat>get mram size MRAM Address Size=3 Partition 0 size=1008, partition 1=523280 MRAM0 size is 0KBytes, MRAM1 size is 512KBytes MRAM2 size is 0KBytes, MRAM3 size is 0KBytes Pacsat>test mram 4 42 NOTE: This test will wipe out the file system and configuration values in MRAM.
Testing with read/write size = 4 bytes, random value base is 0x1864 Write starting at 0KB Write starting at 16KB Write starting at 32KB Write starting at 48KB Write starting at 64KB Write starting at 80KB <skipping a bunch of additional writes> Read starting at 0KB Read starting at 16KB Read starting at 32KB Read starting at 48KB Read starting at 64KB Read starting at 80KB Read starting at 96KB Read starting at 112KB Read starting at 128KB <...> Read starting at 432KB Read starting at 448KB Read starting at 464KB Read starting at 480KB Read starting at 496KB Read starting at 512KB Test is ok! Time is 37 seconds
73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Thu, Feb 8, 2024 at 4:30 PM Bob Stricklin via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote: Ok Burns. Will check soon. At the gym and will be home in about 30 minutes.
Good that you fixed this.
I added 20k pull-up on MOSI and security chip. Also moved the enable lines on the two supply control chips will give details on that later.
Bob
On Feb 8, 2024, at 3:07 PM, Burns Fisher (AMSAT) via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote:
I got one MRAM working, specifically #1. I apparently fixed the chip select for that one.
Please try "get mram sr" with X0.1p. If they say something other than 0xff, they are probably working. Don't mess with the other MRAM commands unless it sees all the MRAMs. I think a lot of that code assumes there are 4 good MRAMs.
In the meantime, I now KNOW that most the SPI bus is ~good on my board, so I'll focus a bit more on the chip selects for 0 and 2. If I have time, I'll see if I can get some of the other tests working for only some MRAMs.
73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Thu, Feb 8, 2024 at 9:20 AM Burns Fisher (AMSAT) <wb1fj@fisher.ccmailto:wb1fj@fisher.cc> wrote: Ok, Bob, glad you figured out how to get the new code.
Regarding the MRAM. I at first thought that you said "okay", but now I think you said zero K. I originally set up the MRAM code to figure out the size of the MRAMs, whether they needed 2 or 3 address bytes, and how many were present. But I only had the one example of Jim's launchpad board, so I'm not surprised it is not quite right for larger MRAMs and especially if the failing MRAMs are not in order (i.e. 0 and 1 work, 2 and 3 do not). But since none work on my board, I could not do anything more. As soon as I can get a board with working MRAMs, I'll fix all that. Also with all the MRAM errors that I get I have disabled a number of the tasks because they quickly failed and reset the processor. I'll fix that when I get a working MRAM board.
Regarding the 5043: Did you do "test ax"? That shows a couple registers from each of the 5043s which we know the value of. I think you can say "get ax 2" to read AX5043 #2, but I'm less sure about that. I did not display all 5 just because I did not know the correct values anyway, and it would just run off the bottom of the screen :-)
More in a separate mailing.
73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Thu, Feb 8, 2024 at 4:17 AM Bob Stricklin via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote: I resolved the issue with GIT I had.
I was setting things up initially with my GIT username and password and apparently you must in CCS.
I have built and run Version ‘o’.
I am seeing data back from 2 of the AX5043s. Probably need to expand code to work with all 4 devices. Later.
get ax returns this …. screen capture
<Screenshot from 2024-02-08 02-56-00.png>
get mram size just returns two of the mram 0 and 2 and indicates their size is 0k. test mram 1 42 seems to run saying Write starting at etc and goes from 0KB to 1024KB. Then it does a Read in same area and does not report any errors but says: Test is OK! Time is 75 seconds. MRAM chips are 4 meg so maybe code only setup for 1 meg.
More testing on hardware later today.
Bob
On Feb 7, 2024, at 10:47 AM, Burns Fisher (AMSAT) <wb1fj@fisher.ccmailto:wb1fj@fisher.cc> wrote:
Yes, the same branch. What errors are you getting? 73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Wed, Feb 7, 2024 at 11:33 AM Bob Stricklin <bstrick@n5brg.commailto:bstrick@n5brg.com> wrote: Burns,
Confirm for me the branch you are working with is WB1FJ_Port_to_Blinky
I am having an issue getting a clean build. I know you were still working CS problem but I am trying to get the GIT build process to work properly.
Bob
On Feb 6, 2024, at 5:34 PM, Bob Stricklin <bstrick@n5brg.commailto:bstrick@n5brg.com> wrote:
OK
Bob
On Feb 6, 2024, at 4:16 PM, Burns Fisher (AMSAT) via pacsat-dev <pacsat-dev@amsat.orgmailto:pacsat-dev@amsat.org> wrote:
I'm reasonably sure that I have the chip select lines screwed up in s/w. I have band rehearsal tonight, so I won't be able to do anything till tomorrow.
73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
On Tue, Feb 6, 2024 at 4:43 PM Burns Fisher (AMSAT) <wb1fj@fisher.ccmailto:wb1fj@fisher.cc> wrote: I added a quick test to tell if the 5043 SPI interface is working. This is in version 0.1n and has been pushed upstream.
Pacsat>test ax AX5043 #0: Revision=7, scratch=7 AX5043 #1: Revision=7, scratch=7 AX5043 #2: Revision=119, scratch=119 AX5043 #3: Revision=7, scratch=7 AX5043 #4: Revision=119, scratch=119 AX5043 #5: Revision=7, scratch=7
This is what it looks like. However the numbers are all wrong. I'm not sure how they can be other than right or 0xff, but something is screwed up. The Revision should be 0x51, which would be printed in decimal as 81. The scratch register, I wrote the AX5043 number into, so each one should read the same as the first number in the line, i.e. 0, 1, 2, 3, 4, 5.
You might as well try it on yours Bob. In the meantime, I'll try to see if I can tell anything on mine.
73,
Burns Fisher, WB1FJ AMSAT(R) Engineering -- Flight Software
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