I've been checking the "sleep" power situation. I put an ammeter in series with ground going to the breadboard which holds only the MRAM. Thus, it should include not only MRAM Vss/Vdd current but also current used via the bus lines. The supply voltage is about 3.25V (the output from the 3.3V line on the Launchpad. Here is what we see with two MR25H40 devices with the clock at 2MHz.
Quiescent Awake: 160 uA
Writing 9.1-9.3mA (This includes sending a WREN (write enable) command for each write command)
MRAM0 asleep, MRAM1 quiescent: 81uA
Both Asleep: 2uA
Reading and writing takes on the order of 50 times as much power as quiescent (you can do the math with more precision)
Quiescent takes relatively little power
Sleep cuts the quiescent power for each MRAM from about 81uA to about 1uA.
So my current thoughts about using sleep:
--Sure it cuts the power use by 98% when the MRAM is not in use.
--But the savings is 98% of a "small" amount: 160uA.
--The savings is only when the MRAM is not in use. (If one is in use and one sleeping, the power reduction is trivial)
--The spec says we must explicitly send a wake command and wait 400uS before we can use an MRAM that is currently asleep. This is a significant time without some additional software.
--The software is a bit less simple than I had hoped; we would have to use a timer and only sleep after a TBD time had passed with no memory ops. If we sleep at each op, the MRAM is hundreds of times slower.
I make no recommendation because the group may decide that the larger number of "CONs" are not as important as the PRO.
I'll check higher clock speeds at some point, but remember that all the power savings above is from quiescent (no clock) to sleep, so I would not expect a difference only in the read/write power.
Burns Fisher, WB1FJ
AMSAT(R) Engineering -- Flight Software