Hi Corey,

I'm not an expert in DSP, but I thought I'd ask some questions.

Do you think moving to a low-IF architecture could assist with the filtering problem? Perhaps by moving the frequency up, you'd lose the need to filter down to so low a frequency. Perhaps centering the IF around 500 kHz or so would allow the low end of your stopband somewhere in the 100's of kHz range. It might be easier to design a filter for that than the baseband design. In combination with the downsampling you mentioned above, maybe you'd have an easier time?

Is there an integrated PLL in the signal processor? Looking at some dedicated DSPs on mouser, it seems that they all have integrated PLLs to meet stability criterion at the frequency of interest. Take a look at this datasheet on page 1476 where it is claiming that the stability of the 8 MHz internal reference is at +/- 1.5%, which would put the error at the maximum VCO frequency (64 MHz) at 960 kHz (by your calculation method). That still seems pretty significant to me. I also noted that they claim you could drive the reference with a crystal, which has much worse stability than a TCXO/OCXO. I think I'm misunderstanding what you're saying, but those are my thoughts.

Thanks,

Cameron

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Cameron Castillo

KJ7ILB

P: (503) 752-8877

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On Tue, Feb 18, 2025 at 5:46 PM Corey Minyard via pacsat-dev <pacsat-dev@amsat.org> wrote:

I'm continuing my learning process on the DSP board. I've learned a few
things:

Baseand filters are a pain. Well, most filters are a pain, but baseband
filters are especially a pain. I couldn't find a pre-made filter that
was really suitable. Well, I found one, but it didn't meet the
temperature range. I have a design using op amps, but it uses 4 op amps
to achieve a transition band that is about the same size as the
passband for a stopband at -60db. That's 4 op amps, each for I and Q in
each direction, so 16 total. At least you can get 2-4 in a package.
The design simulates well in spice, but achieving a sharper filter
appears to be very hard. If that's the case, we will have to sample at
twice the cutoff frequency, basically losing half the bandwidth. So for
a 200KHz bandwidth, we would have to sample at 400KHz and just throw
away the top portion. This is a problem with narrow bandwidths; if you
had a really wide bandwidth then you could use an LC filter and that
would work better. An LC filter with 200KHz cutoff is rather... large.

Second, I don't really understand clocks. In the designs I have done in
telecom you generally just relied on the incoming clocks, but that's not
radio. I found a chip from TI that is a PLL with a VCO and might do the
job, a LMK05318B-Q1, though it's kind of power hungry. Or you could
get programmable oscillators like the DSC8001CL5, but all of those only
seem to go to 150MHz or so. There are fixed oscillators with higher
frequencies. But the amount of error possible in the frequency seems
pretty significant.

But I don't understand about frequency stability. For instance, on the
oscillators that the blinky board is using, you have 16MHz with 2.5PPM
stability. IIUC, that would be +/- 40Hz. But when you multiply that up
to 440MHz, that error would become 1100KHz, which seems pretty
large. Am I understanding this correctly? Is this something to
worry about?

You could compensate in the digital side if you knew what the error was.

Is there anyone I could discuss things with that knows about these sorts
of things? Not much available on the internet.

Thanks,

-corey

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