Thank you, Bob! I could have known / should have known you're already on top of the single event upsets and the latchup aspects of the board. Thank you for confirming all the considerations already present in the layout!

There are still some details to be worked out, some of which depend on the characterization of the initial boards. That makes sense. I'll call out your last point in particular:

"I am sure we have a power issue as I stated earlier. I have been moving ahead to test things with the idea we will have to cut some things back when/if the design moves forward."

Since PACSAT is not yet targeting a specific satellite or launch but is instead looking to build a payload that can be made available for a number of satellites and launches, there won't be a single power budget available. Instead it seems like PACSAT will have a specified power requirement (perhaps a range that can be adjusted by turn on or off features like the number of uplinks).

In defining that range it might be  helpful to consider the target "customer". If targeting the minimum capabilities of 1U CubeSat, I happen to know the average orbit power with fixed cells on all faces is considered 5W with a worst case orbit of 2W. How much of that would a customer be willing to allocate to this subsystem? Perhaps a fair amount if PACSAT is also their primary command and telemetry system (recognizing there will be loss in the electrical power system and other systems are equally important including the command & data handling system and the primary payload)

Or, is a 3U CubeSat a more appropriate target because it will have more power with fixed cells?

I don't have the answer to this question but it's good to be thinking about power as you're already doing,

Jonathan

On 5/20/2023 9:48 PM, Bob Stricklin via pacsat-dev wrote:
Jonathan,

Just looking back through some PacSat-Dev emails and realized I missed this one from you….




On May 5, 2023, at 11:55 AM, Jonathan Brandenburg via pacsat-dev <[email protected]> wrote:

As discussed last night, I've completed some preliminary work on the radiation tolerant circuitry. That does bring up one question...

Bob, do you already have circuitry for watchdog protection and current limiting in the schematic / on the board? Or does that still have to be shoehorned into the board?

Yes, There is a Hardware Watchdog in the schematic and on the PCB - STWD100NYWY3F

Yes, There are several current limit ICs, MAX4495_1 on the bard. The current limit is set by a resistor and is set at 600 mA on each chip. Will need to be tuned to the real value needed after prototyping.


To refine the design I've prototyped, I need to know the anticipated/budgeted power requirements. The part I'm looking at for current limiting, MAX4995AAUT+T, can handle 600mA. If we derate that a bit (are we using 50%?) we can handle 300mA. That's quite a lot so I don't expect an issue with hitting max current except possibly the power amplifier and it's not clear to me if the power amplifier needs to be protected against latchup anyway. In our previous designs, we have a separate current limiter for each AX5043, the power amplifier, and the TMS570. (I think the LNAs are bundled with the AX5043 for the purposes of power limits and peripheral power requirements for TXCOs and such ). I don't think we'll need that many here but we'll probably need one for each voltage rail.


Do we have answers to some of the following questions or is some of still being determined:

1. What power output level are we using on the AX5043? Max current at 16dbm TX is 48 mA plus 6.5 mA for VHF receiver or 9.5 mA for UHF receive.

This is programable in the AX5043 and not currently fix/defined. The AX5043 TX chip is driving a Linear Power section in the design I have because the desire was to have 2 Watts of RF power. PA chip is MMZ09312BT1. We have a Class E output driving a linear power Amp.

2. What LNAs are we using? Does each AX5043 have its own LNA? (I haven't looked for a schematic so tell me to go find it myself if it's in Github.)

LNA is currently a SAV-331+ which should provide about 15 dB of gain. The signal is then filtered and then power converted to a differential signal and split four ways to feed the four AX5043s.

One Receive Antenna is used which feeds the LNA. Then the signal is filtered and converted to differential and power divided  to drive the four AX5043s.

3. What power amplifier are we using and what is the power output? (I still need to double-check a need for current limiter here.)

Output power amp is MMZ09312BT1 (74 Ma) for a total power of about 2 Watts. These are no current limits on the power amps now and they are powered from the main voltage coming to us to get max power.

4. Do we have a characterization for the TMS570 configuration to know which subsystems will be active and thus have a power budget for the TMS570?

No,  The power budget I sent you earlier for all the chips assumes the current posted in the data sheet for each including the TMS570. Probably not going to save a lot of power in this device. You can save power here by running with a slower clock which may support our needs. This can be determined in prototype testing. The clocking for the TMS570 and the AX5043 can be split apart to support rate sensitive functions.


I am sure we have a power issue as I stated earlier. I have beed moving ahead to test things with the idea we will have to cut some things back when/if the design moves forward.

Bob


Thanks a lot!

Jonathan

--
Jonathan Brandenburg, KF5IDY


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