I have been looking through the code and I can force PLLVCOI to 0x92 by setting this value at line 445 of ax5043-ax25.c and commenting out the other lines that write this register. 

However I also see PLLRANGINGA is changing and can be different for device 4 when I read registers. This is in the cal routine I think Burns has been referring too. 

This could be an SPI read issues also?

This area of code is going to need more work. 

Bob

On Apr 25, 2024, at 12:04 PM, Jim McCullers via pacsat-dev <[email protected]> wrote:



Chis,

 

It was showing up at boot and when I executed the test rx command.

I can’t remember if or how much I tested before rewiring the receiver transformers then having the power supply go out.

If I did test it was just for startup and I would have ignored the messages.

 

I’ll reset the RAM once the updated code is in place.

 

Thanks

 

Jim

 

 

Jim,

 

The receiver frequency for each chip is stored in MRAM.  So if you have them set to the same frequency that will stay there.  You need to reset the MRAM to get the defaults.

 

I think a ranging error will show up at boot, printed in the console, but I could be wrong.  

 

73

Chris

 

On Thu, Apr 25, 2024, 12:51 Jim McCullers via pacsat-dev <[email protected]> wrote:

Bob,

I finally got everything back in place and brought Blinky up last night.
I'm getting a ranging error on device 0 and no messages from the others
Same when I attempt the rx command.
All four receivers are showing the same frequency.

I checked this morning and I'm not running the latest code so have it
downloaded and will test tonight if possible.
If it goes well, I'll look into your question.  Technically all four
receives should have the same PLL value as the PLL should range over the two
meter band.
I'll look at that as well.  Have to deep dive into the manual.

I'm suffering from a stiff neck this week and not able to do much.  Always
something!

Jim
WA4CWI

Looking at the feedback from the reading the AX5043 devices I see two have
different PLL vales. The PLL sets the frequency conditions so this may be
involved with the two devices that do not seem to be working.

A listing of the register values reported is attached.

Also the code I think is setting these registers. I have not had time to dig
into the code. If an issue can be seen by someone that has looked at this
code I would appreciate the help.


Bob



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