On Tue, Feb 18, 2025 at 11:23 PM Cameron Castillo via pacsat-dev [email protected] wrote:
Hi Corey,
I'm not an expert in DSP, but I thought I'd ask some questions.
Thanks Cameron. This is more analog, which is probably more up your alley. I'm a lot more familiar with DSP.
Do you think moving to a low-IF architecture could assist with the filtering problem? Perhaps by moving the frequency up, you'd lose the need to filter down to so low a frequency. Perhaps centering the IF around 500 kHz or so would allow the low end of your stopband somewhere in the 100's of kHz range. It might be easier to design a filter for that than the baseband design. In combination with the downsampling you mentioned above, maybe you'd have an easier time?
Well, I guess this is more of a DSP thing. I also don't completely understand what you are saying. I know it's common to have a 455kHz IF, but I'm not sure how it helps here. It would certainly be easier (well, I'd know more about what I'm doing) if this was in the digital realm, but it's not.
For non I/Q D/A and A/D conversion, you have to filter the input signal below the lowest desired frequency (to avoid aliasing), mix it down, then lowpass filter it.
For I/Q demodulation, it's quite a bit different. You don't have to filter out below the desired lowest frequency. Instead you mix down at the middle of the frequency range you are interested in, low pass filter, and since you have I and Q, you can use the negative frequencies. In the digital realm you can upconvert so that all the frequencies are positive. It's a little weird, but it does have some analog parallels in image rejection mixers.
The chip that I found that was ideal (except for temp) was https://www.analog.com/en/products/ltc6602.html but AFAICT it's the only chip that does anywhere near what we would want. I'd also like to have some ability to have multiple possible parts for a job.
Is there an integrated PLL in the signal processor? Looking at some dedicated DSPs on mouser, it seems that they all have integrated PLLs to meet stability criterion at the frequency of interest. Take a look at this datasheet on page 1476 where it is claiming that the stability of the 8 MHz internal reference is at +/- 1.5%, which would put the error at the maximum VCO frequency (64 MHz) at 960 kHz (by your calculation method). That still seems pretty significant to me. I also noted that they claim you could drive the reference with a crystal, which has much worse stability than a TCXO/OCXO. I think I'm misunderstanding what you're saying, but those are my thoughts.
Unfortunately, I need 3 frequencies, one for IF, one for TX, and one for RX. I'm not so concerned about the PLL, but about the oscillator error. I'm not sure my calculation method is correct, either. For FM, I suppose some amount of error isn't too bad and you are having to doppler correct, anyway. I'm more wondering how more normal rigs handle this sort of thing.
-corey
Thanks,
Cameron
Cameron Castillo
KJ7ILB
P: (503) 752-8877
On Tue, Feb 18, 2025 at 5:46 PM Corey Minyard via pacsat-dev [email protected] wrote:
I'm continuing my learning process on the DSP board. I've learned a few things:
Baseand filters are a pain. Well, most filters are a pain, but baseband filters are especially a pain. I couldn't find a pre-made filter that was really suitable. Well, I found one, but it didn't meet the temperature range. I have a design using op amps, but it uses 4 op amps to achieve a transition band that is about the same size as the passband for a stopband at -60db. That's 4 op amps, each for I and Q in each direction, so 16 total. At least you can get 2-4 in a package. The design simulates well in spice, but achieving a sharper filter appears to be very hard. If that's the case, we will have to sample at twice the cutoff frequency, basically losing half the bandwidth. So for a 200KHz bandwidth, we would have to sample at 400KHz and just throw away the top portion. This is a problem with narrow bandwidths; if you had a really wide bandwidth then you could use an LC filter and that would work better. An LC filter with 200KHz cutoff is rather... large.
Second, I don't really understand clocks. In the designs I have done in telecom you generally just relied on the incoming clocks, but that's not radio. I found a chip from TI that is a PLL with a VCO and might do the job, a LMK05318B-Q1, though it's kind of power hungry. Or you could get programmable oscillators like the DSC8001CL5, but all of those only seem to go to 150MHz or so. There are fixed oscillators with higher frequencies. But the amount of error possible in the frequency seems pretty significant.
But I don't understand about frequency stability. For instance, on the oscillators that the blinky board is using, you have 16MHz with 2.5PPM stability. IIUC, that would be +/- 40Hz. But when you multiply that up to 440MHz, that error would become 1100KHz, which seems pretty large. Am I understanding this correctly? Is this something to worry about?
You could compensate in the digital side if you knew what the error was.
Is there anyone I could discuss things with that knows about these sorts of things? Not much available on the internet.
Thanks,
-corey
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On Wed, Feb 19, 2025 at 9:42 AM Corey Minyard [email protected] wrote:
On Tue, Feb 18, 2025 at 11:23 PM Cameron Castillo via pacsat-dev [email protected] wrote:
Hi Corey,
I'm not an expert in DSP, but I thought I'd ask some questions.
Thanks Cameron. This is more analog, which is probably more up your alley. I'm a lot more familiar with DSP.
Do you think moving to a low-IF architecture could assist with the filtering problem? Perhaps by moving the frequency up, you'd lose the need to filter down to so low a frequency. Perhaps centering the IF around 500 kHz or so would allow the low end of your stopband somewhere in the 100's of kHz range. It might be easier to design a filter for that than the baseband design. In combination with the downsampling you mentioned above, maybe you'd have an easier time?
Well, I guess this is more of a DSP thing. I also don't completely understand what you are saying. I know it's common to have a 455kHz IF, but I'm not sure how it helps here. It would certainly be easier (well, I'd know more about what I'm doing) if this was in the digital realm, but it's not.
I thought about this some more and played around with filters last night. You can build a surprisingly tight filter at IF frequencies, so filtering at IF might ease the burden on the filters at baseband. Not at 500kHz (that's actually about the bandwidth I'm looking at) but at 40MHz or so.
-corey
For non I/Q D/A and A/D conversion, you have to filter the input signal below the lowest desired frequency (to avoid aliasing), mix it down, then lowpass filter it.
For I/Q demodulation, it's quite a bit different. You don't have to filter out below the desired lowest frequency. Instead you mix down at the middle of the frequency range you are interested in, low pass filter, and since you have I and Q, you can use the negative frequencies. In the digital realm you can upconvert so that all the frequencies are positive. It's a little weird, but it does have some analog parallels in image rejection mixers.
The chip that I found that was ideal (except for temp) was https://www.analog.com/en/products/ltc6602.html but AFAICT it's the only chip that does anywhere near what we would want. I'd also like to have some ability to have multiple possible parts for a job.
Is there an integrated PLL in the signal processor? Looking at some dedicated DSPs on mouser, it seems that they all have integrated PLLs to meet stability criterion at the frequency of interest. Take a look at this datasheet on page 1476 where it is claiming that the stability of the 8 MHz internal reference is at +/- 1.5%, which would put the error at the maximum VCO frequency (64 MHz) at 960 kHz (by your calculation method). That still seems pretty significant to me. I also noted that they claim you could drive the reference with a crystal, which has much worse stability than a TCXO/OCXO. I think I'm misunderstanding what you're saying, but those are my thoughts.
Unfortunately, I need 3 frequencies, one for IF, one for TX, and one for RX. I'm not so concerned about the PLL, but about the oscillator error. I'm not sure my calculation method is correct, either. For FM, I suppose some amount of error isn't too bad and you are having to doppler correct, anyway. I'm more wondering how more normal rigs handle this sort of thing.
-corey
Thanks,
Cameron
Cameron Castillo
KJ7ILB
P: (503) 752-8877
On Tue, Feb 18, 2025 at 5:46 PM Corey Minyard via pacsat-dev [email protected] wrote:
I'm continuing my learning process on the DSP board. I've learned a few things:
Baseand filters are a pain. Well, most filters are a pain, but baseband filters are especially a pain. I couldn't find a pre-made filter that was really suitable. Well, I found one, but it didn't meet the temperature range. I have a design using op amps, but it uses 4 op amps to achieve a transition band that is about the same size as the passband for a stopband at -60db. That's 4 op amps, each for I and Q in each direction, so 16 total. At least you can get 2-4 in a package. The design simulates well in spice, but achieving a sharper filter appears to be very hard. If that's the case, we will have to sample at twice the cutoff frequency, basically losing half the bandwidth. So for a 200KHz bandwidth, we would have to sample at 400KHz and just throw away the top portion. This is a problem with narrow bandwidths; if you had a really wide bandwidth then you could use an LC filter and that would work better. An LC filter with 200KHz cutoff is rather... large.
Second, I don't really understand clocks. In the designs I have done in telecom you generally just relied on the incoming clocks, but that's not radio. I found a chip from TI that is a PLL with a VCO and might do the job, a LMK05318B-Q1, though it's kind of power hungry. Or you could get programmable oscillators like the DSC8001CL5, but all of those only seem to go to 150MHz or so. There are fixed oscillators with higher frequencies. But the amount of error possible in the frequency seems pretty significant.
But I don't understand about frequency stability. For instance, on the oscillators that the blinky board is using, you have 16MHz with 2.5PPM stability. IIUC, that would be +/- 40Hz. But when you multiply that up to 440MHz, that error would become 1100KHz, which seems pretty large. Am I understanding this correctly? Is this something to worry about?
You could compensate in the digital side if you knew what the error was.
Is there anyone I could discuss things with that knows about these sorts of things? Not much available on the internet.
Thanks,
-corey
pacsat-dev mailing list -- [email protected] View archives of this mailing list at https://mailman.amsat.org/hyperkitty/list/[email protected] To unsubscribe send an email to [email protected] Manage all of your AMSAT-NA mailing list preferences at https://mailman.amsat.org
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Corey Minyard